Processors : Cache Line Store Matrix (c)RS
Cache Line Store Matrix (c)RS
The consideration of the EdgeTPU allows one to observe that the equivalence of the Intel Movidius & the EdgeTPU in 8 Bit functions are the application of parallel groups of 8Bit Inferencing Parallel Matrix
A matrix example is:
*, +, *+, Cache Line Store Matrix (c)RS
Example 5 rows Vertical & 5 Horizontal
Matrix operation formulas are representative of a matrix,
Matrix formulas are based on school matrix algebra maths as studied by myself at school,
Most maths & physics / Sciences students would be familiar with the formulas of matrix maths, Although advanced.. & complex,.. Or simple!
You may be aware that Apple, ARM, Intel & so forth variants exist, including the NPU!
You may be aware that the basic process allows pre formula & extended after formulas..
Indeed strategically the NPU & SVE AVX & SiMD variants are typically allied with maths arrays & SiMD maths formulas..
You may be aware that in principle matrix maths may be alloyed with maths functions & that all are useful with a GPU, CPU or FPGA formula..
You may be aware that they are used for 3D, Audio, Video, Maths & Machine Learning...
Indeed this is the plan!
M = Matrix
C=Processor Complex
D=Extende functions such as SiMD
Suggested Schematic Matrix Array!
M,M,M,D
C,C,C,D
M,M,M,D
(c)Rupert S
Reference
https://is.gd/SVG_DualBlend https://is.gd/MediaSecurity https://is.gd/JIT_RDMA
https://is.gd/PackedBit https://is.gd/BayerDitherPackBitDOT
https://is.gd/QuantizedFRC https://is.gd/BlendModes https://is.gd/TPM_VM_Sec
https://is.gd/IntegerMathsML https://is.gd/ML_Opt https://is.gd/OPC_ML_Opt https://is.gd/OPC_ML_QuBit https://is.gd/QuBit_GPU https://is.gd/NUMA_Thread
On the subject of how deep a personality of 4Bit, 8Bit, 16Bit is reference:
https://science.n-helix.com/2021/03/brain-bit-precision-int32-fp32-int16.html
https://science.n-helix.com/2022/10/ml.html
